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11.1Gb/s Lane Extender
ISL36111
The ISL36111 is a settable single-channel receive-side equalizer with extended functionality for advanced protocols operating with line rates up to 11.1Gb/s such as 10G Ethernet. The ISL36111 compensates for the frequency dependent attenuation of copper twin-axial cables, extending the signal reach up to at least 10m on 28AWG cable. The small form factor, highly-integrated design is ideal for high-density data transmission applications including active copper cable assemblies. The equalizing filter within the ISL36111 can be set to provide optimal signal fidelity for a given media and length. The compensation level for the filter is set by two external control pins. Operating on a single 1.2V power supply, the ISL36111 enables channel throughputs of 10Gb/s to 11.1Gb/s while supporting lower data rates including 8.5, 6.25, 5, 4.25, 3.125, and 2.5Gb/s. The ISL36111 uses current mode logic (CML) input/output and is packaged in a 3mmx3mm 16 lead QFN. The device supports LOS functionality for module applications.
ISL36111
Features
* Supports data rates up to 11.1Gb/s * Low power (~110mW) * Low latency (<500ps) * Single channel equalizer in a 3mmx3mm QFN package for straight route-through architecture and simplified routing * Adjustable equalizer boost * Supports 64b/66b encoded data - long run lengths * Line silence preservation * 1.2V supply voltage * Loss of Signal support
Applications
* SFP+ active copper cable modules * QSFP active copper cable modules * 10G Ethernet * Fibre Channel * High-speed active cable assemblies * High-speed printed circuit board (PCB) traces
Benefits
* Thinner gauge cable * Extends cable reach greater than 3x * Improved BER
Typical Application Diagram
1.2V 1.2V
LOS 0.1mF
CP-A CP-B
Vdd 0.1mF 0.1mF
LOS IN [P]
Vdd DE-A DE-B OUT [P]
OUT [P] 0.1mF
IN [P] 0.1mF
ISL36111 QLx111VRx
OUT [N] GND IN [N] DT
0.1mF
ISL35111 QLx111VTx
IN [N] TDSBL GND OUT [N] DT
FIGURE 1. TYPICAL CABLE APPLICATION DIAGRAM
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL36111
Ordering Information
PART NUMBER (Notes 1, 2, 3) ISL36111DRZ-TS ISL36111DRZ-T7 NOTES: 1. "-TS" and "-T7" suffix is for Tape and Reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL36111. For more information on MSL please see techbrief TB363. PART MARKING 6111 6111 TEMP. RANGE (C) 0 to +85 0 to +85 PACKAGE (Pb-Free) 16 Ld QFN (7'' 100 pcs.) 16 Ld QFN (7" 1k pcs.) PKG. DWG. # L16.3x3B L16.3x3B
Pin Configuration
ISL36111 (16 LD QFN) TOP VIEW
GND GND 13 12 VDD 11 OUT[P] 10 OUT[N] 9 5 GND 6 CPA 7 CPB 8 GND VDD NC 14
16 VDD 1 IN[P] 2 IN[N] 3 LOSB 4
Pin Descriptions
PIN NAME VDD IN[P,N] LOSB CP[A,B,] GND OUT[P,N] DT PIN NUMBER 1, 9, 12 2, 3 4 6, 7 5, 8, 13, 16 11, 10 15 DESCRIPTION Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to ground is recommended for each of these pins for broad high-frequency noise suppression. Equalizer differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. LOS BAR indicator. Low output when input signal is below DT threshold. This pin is internally pulled HIGH with an 11k resistor. Control pins for setting equalizer boost level. Tri-state inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and B is the LSB. These pins must be grounded. Equalizer differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. Detection Threshold. Reference DC voltage threshold for input signal power detection. Data output OUT[P,N] is muted when the power of the input signal IN[P,N] falls below the threshold. Tie to ground to disable electrical idle preservation and always enable the output driver. Exposed pad. For proper electrical and thermal performance, this pad should be connected to the PCB ground plane.
Exposed Pad
-
2
DT 15
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ISL36111
Absolute Maximum Ratings
Supply Voltage (VDD to GND) Voltage at All Input Pins . . . . ESD Rating High-Speed Pins . . . . . . . . All Other Pins . . . . . . . . . . . . . . . . . . . . . . -0.3V to 1.5V . . . . . . . . . . . . -0.3V to 1.5V . . . . . . . . . . . . . 1.5kV (HBM) . . . . . . . . . . . . . . 2kV (HBM)
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 16 Ld QFN Package (Notes 4, 5) . . 56 10 Operating Ambient Temperature Range . . . . . . 0C to +85C Storage Ambient Temperature Range . . . . -55C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . +125C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 4. JA measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Operating Conditions
PARAMETER Supply Voltage Operating Ambient Temperature Bit Rate SYMBOL VDD TA NRZ data applied to any channel CONDITION MIN 1.1 0 2.5 TYP 1.2 25 MAX 1.3 85 11.1 UNITS V C Gb/s
Control Pin Characteristics VDD = 1.2V, TA = +25C, and VIN = 600mVP-P, unless otherwise noted.
PARAMETER Output LOW Logic Level Output HIGH Logic Level Input Current SYMBOL VOL VOH LOSB LOSB Current draw on boost control pin, i.e., CP[A,B] CONDITION MIN 0 1000 30 TYP 0 MAX 250 VDD 100 UNITS mV mV A
Electrical Specifications
PARAMETERS Supply Current Cable Input Amplitude Range IDD VIN
VDD = 1.2V, TA = +25C, and VIN = 600mVP-P, unless otherwise noted. CONDITION Measured differentially at data source before encountering channel loss; Up to 10m 28AWG standard twin-axial cable (approx. -27dB @ 5GHz) Measured on input channel IN[P,N] Measured on input channel IN[P] or IN[N], with respect to VDD. MIN 600 TYP 92 1600 MAX UNITS mA mVP-P 6 NOTES
SYMBOL
DC Differential Input Resistance DC Single-Ended Input Resistance Input Return Loss Limit (Differential) Output Amplitude Range Differential Output Impedance Output Return Loss Limit (Differential) Output Return Loss Limit (Common Mode) Output Residual Jitter SDD22 SCC22 SDD11 VOUT
80 40
100 50 Note 7 Note 8
120 60
dB dB 7 8
100MHz to 4.1GHz 4.1GHz to 11.1GHz Measured differentially at OUT[P] and OUT[N] with 50 load on both output pins Measured on OUT[P,N] 100MHz to 4.1GHz 4.1GHz to 11.1GHz 100MHz to 2.5GHz 2.5GHz to 11.1GHz 10.3125Gbps; Up to 10m 28AWG standard twin-axial cable (approx. -27dB @ 5GHz) 450 80
650 105 Note 7 Note 8 Note 9 -3 0.35
850 120
mVP-P dB dB dB dB UI 7 8 9 10 6, 11, 12
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ISL36111
Electrical Specifications
PARAMETERS Output Transition Time Propagation Delay NOTES: 6. The input pins IN[P,N] are DC biased to VDD. The specified cable input amplitude range is established by characterization and not production tested, and is valid so long as the voltages at the input pins IN[P,N] do not violate the voltage ranges specified in "Absolute Maximum Ratings" on page 3. 7. Maximum Reflection Coefficient given by equation SDDXX(dB) = -12 + 2*(f), with f in GHz. Established by characterization and not production tested. 8. Maximum Reflection Coefficient given by equation SDDXX(dB) = -6.3 + 13Log10(f/5.5), with f in GHz. Established by characterization and not production tested. 9. Reflection Coefficient given by equation SCCXX(dB) < -7 + 1.6*f, with f in GHz. Established by characterization and not production tested. 10. Limits established by characterization and are not production tested. 11. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted signal (as measured at the input to the channel). Total jitter (TJ) is DJpp + 14.1 x RJRMS 12. Measured using a PRBS 215-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent, media-induced loss only. tr, tf VDD = 1.2V, TA = +25C, and VIN = 600mVP-P, unless otherwise noted. (Continued) CONDITION 20% to 80% From IN to OUT MIN TYP 32 500 MAX UNITS ps ps NOTES 13
SYMBOL
13. Rise and fall times measured using a 2GHz clock with a 20ps edge rate.
Typical Performance Characteristics
Performance is measured using the test setup illustrated in Figure 2. The signal from the pattern generator is launched into the twin-ax cable using an SMA adapter card. The chip evaluation board is connected to the output of the cable through another adapter card. The ISL36111 output signal is then visualized on a scope to determine signal integrity parameters such as jitter.
Pattern Generator
SMA Adapter Card
100O Twin-Axial Cable
SMA Adapter Card
ISL36111 Eval Board
Oscilloscope
FIGURE 2. DEVICE CHARACTERIZATION SET UP
FIGURE 3. ISL36111 10.3125Gb/s OUTPUT FOR A 10M 28AWG CABLE
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ISL36111
CPA CPB
Limiting Amplifier IN[P] IN[N] Signal Detector Adjustable Equalizer
Output Driver OUT[P] OUT[N]
DT
LOSB
FIGURE 4. FUNCTIONAL BLOCK DIAGRAM OF THE ISL36111
Operation
The ISL36111 is an advanced lane-extender for high-speed interconnects. A functional diagram of ISL36111 is shown in Figure 4. In addition to a robust equalization filter to compensate for channel loss and restore signal fidelity, the ISL36111 contains unique integrated features to preserve special signaling protocols typically broken by other equalizers. The signal detect function is used to mute the channel output when the input signal falls below the level determined by the Detection Threshold (DT) pin voltage. This function is intended to preserve periods of line silence ("DC idle"). Furthermore, the output of the Signal Detect/DT comparator is used as a loss of signal (LOSB) indicator to indicate the absence of a received signal. As illustrated in Figure 4, the core of the high-speed signal path in the ISL36111 is a sophisticated equalizer followed by a limiting amplifier. The equalizer compensates for skin loss, dielectric loss, and impedance discontinuities in the transmission channel. The equalizer is followed by a limiting amplification stage that provides a clean output signal with full amplitude swing and fast rise-fall times for reliable signal decoding in a subsequent receiver.
TABLE 1. MAPPING BETWEEN BOOST LEVEL AND CP-PIN CONNECTIVITY CPA Float Float GND Float VDD GND GND VDD VDD CPB Float GND VDD VDD Float Float GND GND VDD BOOST LEVEL 0 1 2 3 4 5 6 7 8
CML Input and Output Buffers
The input and output buffers for the high-speed data channel in the ISL36111 are implemented using CML. Equivalent input and output circuits are shown in Figures 5 and 6.
V DD
Adjustable Equalization Boost
ISL36111 features a settable equalizer for custom signal restoration. The flexibility of this adjustable compensation architecture enables signal fidelity to be optimized based on a given application, providing support for a wide variety of channel characteristics and data rates ranging from 2.5Gb/s to 11.1Gb/s. Because the boost level is externally set rather than internally adapted, the ISL36111 provides reliable communication from the very first bit transmitted. There is no time needed for adaptation and control loop convergence. Furthermore, there are no pathological data patterns that will cause the ISL36111 to move to an incorrect boost level.
IN[P]
50O
1st Filter Stage
50O
IN[N]
Control Pin Boost Setting
The connectivity of the CP pins are used to determine the boost level of ISL36111. Table 1 defines the mapping from the 2-bit CP word to the 9 available boost levels. 5
FIGURE 5. CML INPUT EQUIVALENT CIRCUIT FOR THE ISL36111
FN6974.0 November 19, 2009
ISL36111
VDD
11k
LOSB
Internal LOS Indicator
FIGURE 6. CML OUTPUT EQUIVALENT CIRCUIT FOR THE ISL36111
FIGURE 7. LOSB EQUIVALENT OUTPUT STRUCTUR
Line Silence/Quiescent Mode
Line silence is commonly broken by the limiting amplification in other equalizers. This disruption can be detrimental in many systems that rely on line silence as part of the protocol. The ISL36111 contains special lane management capabilities to detect and preserve periods of line silence while still providing the fidelity-enhancing benefits of limiting amplification during active data transmission. Line silence is detected by measuring the amplitude of the input signal and comparing that to a threshold set by the voltage at the DT pin. When the amplitude falls below the threshold, the output driver stage is muted.
Detection Thereshold (DT) Pin Functionality
The ISL36111 is capable of maintaining periods of line silence by monitoring the channel for loss of signal (LOS) conditions and subsequently muting the output driver when such a condition is detected. A reference voltage applied to the detection threshold (DT) pin is used to set the LOS threshold of the internal signal detection circuitry. The DT voltage is set with an external pull-up resistor, RDT. For typical applications, a 30k resistor is recommended for channels with loss greater than 12dB at 5GHz, and a 1.8k resistor is recommended for lower loss channels. Other values of the resistor may also be applicable; therefore DT settings should be verified on an application-specific basis.
LOS Bar Indicator
Pin 4 (LOSB) is used to output the state of the muting circuitry to serve as a loss of signal indicator for the device. This signal is directly derived from the muting signal output by the detection threshold / signal detector comparator. The LOSB signal goes LOW when the signal detector output is below the externally controlled detection threshold and HIGH when the detector output goes above this threshold. This feature is meant to be used in optical systems (e.g. SFP+) where there are no quiescent or electrical-idle states. In these cases, the detection threshold is used to determine the sensitivity of the LOSB indicator. Figure 7 shows the schematic of the LOSB equivalent output structure.
About Q:ACTIVE(R)
Intersil has long realized that to enable the complex server clusters of next generation datacenters, it is critical to manage the signal integrity issues of electrical interconnects. To address this, Intersil has developed its groundbreaking Q:ACTIVE(R) product line. By integrating its analog ICs inside cabling interconnects, Intersil is able to achieve unsurpassed improvements in reach, power consumption, latency, and cable gauge size as well as increased airflow in tomorrow's datacenters. This new technology transforms passive cabling into intelligent "roadways" that yield lower operating expenses and capital expenditures for the expanding datacenter. Intersil Lane Extenders allow greater reach over existing cabling while reducing the need for thicker cables. This significantly reduces cable weight and clutter, increases airflow, and improves power consumption.
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FN6974.0 November 19, 2009
ISL36111
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 11/19/09 REVISION FN6974.0 Initial Release to web CHANGE
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL36111 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 7
FN6974.0 November 19, 2009
ISL36111
Package Outline Drawing
L16.3x3B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 4/07
4X 1.5 3.00 A B 6 PIN 1 INDEX AREA 13 12X 0.50 16 6 PIN #1 INDEX AREA
12
1
3.00
1 .70
+ 0.10 - 0.15
9
4
(4X)
0.15 8 5 0.10 M C A B 4 16X 0.23 - 0.05 16X 0.40 0.10
+ 0.07
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 0.1 BASE PLANE ( 2. 80 TYP )
C
SEATING PLANE 0.08 C
SIDE VIEW
( 1. 70 ) ( 12X 0 . 5 )
( 16X 0 . 23 ) C 0 . 2 REF
5
( 16X 0 . 60)
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
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